Various techniques for allowing simultaneous access to a memory are known in the art. For example, U.S. Pat. No. 8,514,651, whose disclosure is incorporated herein by reference, describes a memory device having a set of memory banks to store content data. At least two requests to perform respective read memory operations in a first memory bank are received during a single clock cycle. One or more of the at least two requests are blocked from accessing the first memory bank, and in response: redundancy data associated with the first memory bank and different from content data stored therein is accessed, and, without accessing the first memory bank, at least a portion of the content data stored in the first memory bank is reconstructed based on the associated redundancy data. A first memory read operation is performed using the content data stored in the first memory bank, and a second memory read operation is performed using content data reconstructed i) without accessing the first memory bank and ii) based on the associated redundancy data.
The description above is presented as a general overview of related art in this field and should not be construed as an admission that any of the information it contains constitutes prior art against the present patent application.